000			03235cam a22004815i 4500
001			8560851
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005			20211027154431.0
006			m d
007			cr n
008			100927s2011 xxu| s |||| 0|eng d
020			_a9781441979278
024	7		_a10.1007/978-1-4419-7928-5 _2doi
035			_a(WaSeSS)ssj0000449030
038			_akhadija
040			_dWaSeSS _c.
050		4	_aTK7888.4
050		4	_aTK7895.G36
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.395 _223 _bPAR
100	1		_aParvez, Husain. _eauthor. _983473
210	1	0	_aApplication-Specific Mesh-based Heterogeneous FPGA Architectures
245	1	0	_aApplication-Specific Mesh-based Heterogeneous FPGA Architectures / _cby Husain Parvez, Habib Mehrez.
505	0		_aIntroduction -- State of the Art -- FPGA Layout Generation -- ASIF: Application Specific Inflexible FPGA -- ASIF using Heterogeneous Logic Blocks -- ASIF Hardware Generation -- Conclusion and Future Lines of Research.
506			_aLicense restrictions may limit access.
520			_aLow volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However, the flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs. Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption. This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures. Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures; Describes state-of-the-art techniques for reducing area requirements in FPGA architectures; Enables reduction in power required and increase in performance.
563			_aHardcover
650		0	_aEngineering.
650		0	_aElectronics.
650		0	_aSystems engineering. _91386
650	1	4	_aEngineering. _983474
650	2	4	_aCircuits and Systems. _981558
650	2	4	_aElectronics and Microelectronics, Instrumentation. _983475
700	1		_aMehrez, Habib. _eauthor. _983476
710	2		_aSpringerLink (Online service) _981564
773	0		_tSpringer eBooks
773		0	_tSpringerLink ebooks - Engineering (2011)
776	0	8	_iPrinted edition: _z9781441979278
856	4	0	_uhttp://www.columbia.edu/cgi-bin/cul/resolve?clio8560851 _zFull text available from SpringerLink ebooks - Engineering (2011)
910			_aVendor-generated brief record
942			_2ddc _cBK
999			_c32911 _d32911