000			01454 a2200193 4500
020			_a8129700921
040			_aDLC _bDLC
082	0	0	_a621.392
100	1		_aPalnitkar, Samir.
245	1	0	_aVerilog HDL: a guide to digital design and synthesis _ba guide to digital design and synthesis _cSamir Palnitkar
250			_a2nd ed.
260			_aUpper Saddle River, NJ : _bSunSoft Press, _cc2003.
300			_axlii, 490 p. : _bill. ; _c25 cm. +
500			_a"A Prentice Hall title."
500			_a"Professional technical reference"--P. [4] cover.
505	0		_aPt. 1. Basic Verilog Topics -- 1. Overview of Digital Design with Verilog HDL -- 2. Hierarchical Modeling Concepts -- 3. Basic Concepts -- 4. Modules and Ports -- 5. Gate-Level Modeling -- 6. Dataflow Modeling -- 7. Behavioral Modeling -- 8. Tasks and Functions -- 9. Useful Modeling Techniques -- Pt. 2. Advanced Verilog Topics -- 10. Timing and Delays -- 11. Switch-Level Modeling -- 12. User-Defined Primitives -- 13. Programming Language Interface -- 14. Logic Synthesis with Verilog HDL -- 15. Advanced Verification Techniques -- Pt. 3. Appendices -- App. A. Strength Modeling and Advanced Net Definitions -- App. B. List of PLI Routines -- App. C. List of Keywords, System Tasks, and Compiler Directives -- App. D. Formal Syntax Definition -- App. E. Verilog Tidbits -- App. F. Verilog Examples.
650		0	_aVerilog (Computer hardware description language)
942			_cBK _k621.392 PAL _2ddc
999			_c4778 _d4778