000			00903 a2200205 4500
020			_a0071445641
040			_aDLC _bDLC
082	0	0	_a621.392
100	1		_aNavabi, Zainalabedin.
245	1	0	_aVerilog digital system design: RT level synthesis, testbench and verification _bRT level synthesis, testbench and verification _cZainalabedin Navabi.
250			_a2nd ed.
260			_aNew York : _bMcGraw-Hill, _cc2006.
300			_axvi, 384 p. : _bill. ; _c24 cm. + _e1 CD-ROM (4 3/4 in.)
490	1		_aMcGraw-Hill electronic engineering
650		0	_aVerilog (Computer hardware description language)
650		0	_aElectronic digital computers _xComputer-aided design.
856	4	2	_3Publisher description _uhttp://www.loc.gov/catdir/enhancements/fy0668/2006271457-d.html
856	4	2	_3Table of contents only _uhttp://www.loc.gov/catdir/enhancements/fy0668/2006271457-t.html
942			_cBK _k621.392 NAV _2ddc
999			_c9539 _d9539